/*
 * Copyright (C) 1999-2013, Broadcom Corporation 
 *  
 *      Unless you and Broadcom execute a separate written software license 
 * agreement governing use of this software, this software is licensed to you 
 * under the terms of the GNU General Public License version 2 (the "GPL"), 
 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 
 * following added to such license: 
 *  
 *      As a special exception, the copyright holders of this software give you 
 * permission to link this software with independent modules, and to copy and 
 * distribute the resulting executable under terms of your choice, provided that 
 * you also meet, for each linked independent module, the terms and conditions of 
 * the license of that module.  An independent module is a module which is not 
 * derived from this software.  The special exception does not apply to any 
 * modifications of the software. 
 *  
 *      Notwithstanding the above, under no circumstances may you combine this 
 * software in any way with any other Broadcom software provided under a license 
 * other than the GPL, without Broadcom's express prior written consent. 
 */
/***************************************************************************
 *     Copyright (c) 1999-2011, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: local_ddr23_ctl_regs_0.h $
 * $brcm_Revision: cfe_bdvd_andover/2 $
 * $brcm_Date: 8/11/11 12:14p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Tue Jan 18 17:15:06 2011
 *                 MD5 Checksum         1fb6ed1392ca34b0950e37060abe0b3b
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /rockford/bsp/Shmoo/ddr40phy/include/local_ddr23_ctl_regs_0.h $
 * 
 * cfe_bdvd_andover/2   8/11/11 12:14p ckder
 * SWBLURAY-26789:[ see Broadcom Issue Tracking JIRA for more info ].
 * 
 * cfe_bdvd_andover/dev_cfe_bdvd_andover_SWBLURAY-26789/1   8/9/11 9:26a ckder
 * Checkpoint before MTEST_PARMS
 * 
 * cfe_bdvd_andover/1   8/2/11 11:31a ckder
 * SWBLURAY-26732:[ see Broadcom Issue Tracking JIRA for more info ].
 * Initial checkin to Clearcase - pre-release files for the record only.
 * 
 * dev_cfe_bdvd_andover_SWBLURAY-26732/1   7/29/11 4:01p ckder
 * Generic SHMOO release 0
 * 
 * Hydra_Software_Devel/2   1/20/11 6:36p etrudeau
 * SWBLURAY-24294: remove -no_bits and no_align from second combo_headers
 * pass and add bchp_ddr to files to take from second pass
 *
 ***************************************************************************/

#ifndef BCHP_DDR23_CTL_REGS_0_H__
#define BCHP_DDR23_CTL_REGS_0_H__

/***************************************************************************
 *DDR23_CTL_REGS_0 - DDR23 controller registers
 ***************************************************************************/
#define BCHP_DDR23_CTL_REGS_0_REVISION           0x00000000 /* DDR23 Controller revision register */
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS         0x00000004 /* DDR23 Controller status register */
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS         0x00000008 /* 40G DDR PHY status register */
#define BCHP_DDR23_CTL_REGS_0_PARAMS1            0x00000010 /* DDR23 Controller Configuration Set #1 */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2            0x00000014 /* DDR23 Controller Configuration Set #2 */
#define BCHP_DDR23_CTL_REGS_0_PARAMS3            0x00000018 /* DDR23 Controller Configuration Set #3 */
#define BCHP_DDR23_CTL_REGS_0_REFRESH            0x0000001c /* DDR23 Controller Automated Refresh Configuration */
#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD        0x00000020 /* Host Initiated Refresh Control */
#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD      0x00000024 /* Host Initiated Precharge Control */
#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD      0x00000028 /* Host Initiated Load Mode Control */
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD     0x0000002c /* Host Initiated Load Extended Mode Control */
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD    0x00000030 /* Host Initiated Load Extended Mode #2 Control */
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD    0x00000034 /* Host Initiated Load Extended Mode #3 Control */
#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE       0x00000038 /* Host Initiated ZQ Calibration Cycle */
#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS         0x0000003c /* Host Command Interface Status */
#define BCHP_DDR23_CTL_REGS_0_LATENCY            0x00000040 /* DDR2 Controller Access Latency Control */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0         0x00000044 /* Semaphore Register #0 */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1         0x00000048 /* Semaphore Register #1 */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2         0x0000004c /* Semaphore Register #2 */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3         0x00000050 /* Semaphore Register #3 */
#define BCHP_DDR23_CTL_REGS_0_SCRATCH            0x00000058 /* Scratch Register */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH       0x00000060 /* Stripe Width */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0    0x00000070 /* Stripe Height for picture buffers 0 through 23 */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1    0x00000074 /* Stripe Height for picture buffers 24 through 27 */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2    0x00000078 /* Stripe Height for picture buffers 28 through 31 */
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG         0x00000080 /* PLL Configuration Register */
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS         0x00000084 /* PLL Status Register */
#define BCHP_DDR23_CTL_REGS_0_PLL_CONTROL        0x00000088 /* PLL Control Register */
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL   0x0000008c /* PLL Gain Control Register */
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS       0x00000090 /* PLL Dividers Register */
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL     0x00000094 /* PLL Spread Spectrum Control Register */
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_LIMIT       0x00000098 /* PLL Spread Spectrum Limit Register */
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_STEP        0x0000009c /* PLL Spread Spectrum Step Register */
#define BCHP_DDR23_CTL_REGS_0_VDL_CTL            0x000000b0 /* Dynamic VDL Changes Control */
#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_BASE       0x000000b4 /* Dynamic VDL Changes Base Address */
#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_END        0x000000b8 /* Dynamic VDL Changes End Address */
#define BCHP_DDR23_CTL_REGS_0_PMON_CTL           0x000000c0 /* Performance Monitoring Control */
#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD        0x000000c4 /* Performance Monitoring Period Control */
#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT     0x000000c8 /* Performance Monitoring Active Cycles Count */
#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT      0x000000cc /* Performance Monitoring Idle Cycles Count */
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1       0x000000d0 /* Performance Monitoring Data Channel #1 Read Accesses Count */
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2       0x000000d4 /* Performance Monitoring Data Channel #2 Read Accesses Count */
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3       0x000000d8 /* Performance Monitoring Data Channel #3 Read Accesses Count */
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1       0x000000dc /* Performance Monitoring Data Channel #1 Write Accesses Count */
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2       0x000000e0 /* Performance Monitoring Data Channel #2 Write Accesses Count */
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3       0x000000e4 /* Performance Monitoring Data Channel #3 Write Accesses Count */
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL         0x000000f0 /* RAM Macro TM Control */

/***************************************************************************
 *REVISION - DDR23 Controller revision register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: REVISION :: reserved0 [31:16] */
#define BCHP_DDR23_CTL_REGS_0_REVISION_reserved0_MASK              0xffff0000
#define BCHP_DDR23_CTL_REGS_0_REVISION_reserved0_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_REVISION_reserved0_BITS              16
#define BCHP_DDR23_CTL_REGS_0_REVISION_reserved0_SHIFT             16

/* DDR23_CTL_REGS_0 :: REVISION :: MAJOR [15:08] */
#define BCHP_DDR23_CTL_REGS_0_REVISION_MAJOR_MASK                  0x0000ff00
#define BCHP_DDR23_CTL_REGS_0_REVISION_MAJOR_ALIGN                 0
#define BCHP_DDR23_CTL_REGS_0_REVISION_MAJOR_BITS                  8
#define BCHP_DDR23_CTL_REGS_0_REVISION_MAJOR_SHIFT                 8

/* DDR23_CTL_REGS_0 :: REVISION :: MINOR [07:00] */
#define BCHP_DDR23_CTL_REGS_0_REVISION_MINOR_MASK                  0x000000ff
#define BCHP_DDR23_CTL_REGS_0_REVISION_MINOR_ALIGN                 0
#define BCHP_DDR23_CTL_REGS_0_REVISION_MINOR_BITS                  8
#define BCHP_DDR23_CTL_REGS_0_REVISION_MINOR_SHIFT                 0

/***************************************************************************
 *CTL_STATUS - DDR23 Controller status register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: CTL_STATUS :: reserved0 [31:07] */
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved0_MASK            0xffffff80
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved0_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved0_BITS            25
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved0_SHIFT           7

/* DDR23_CTL_REGS_0 :: CTL_STATUS :: rd_fifo3_empty [06:06] */
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo3_empty_MASK       0x00000040
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo3_empty_ALIGN      0
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo3_empty_BITS       1
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo3_empty_SHIFT      6

/* DDR23_CTL_REGS_0 :: CTL_STATUS :: rd_fifo2_empty [05:05] */
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo2_empty_MASK       0x00000020
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo2_empty_ALIGN      0
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo2_empty_BITS       1
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo2_empty_SHIFT      5

/* DDR23_CTL_REGS_0 :: CTL_STATUS :: rd_fifo1_empty [04:04] */
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo1_empty_MASK       0x00000010
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo1_empty_ALIGN      0
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo1_empty_BITS       1
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo1_empty_SHIFT      4

/* DDR23_CTL_REGS_0 :: CTL_STATUS :: reserved1 [03:02] */
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved1_MASK            0x0000000c
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved1_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved1_BITS            2
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved1_SHIFT           2

/* DDR23_CTL_REGS_0 :: CTL_STATUS :: clke [01:01] */
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_MASK                 0x00000002
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_ALIGN                0
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_BITS                 1
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_SHIFT                1

/* DDR23_CTL_REGS_0 :: CTL_STATUS :: idle [00:00] */
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK                 0x00000001
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_ALIGN                0
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_BITS                 1
#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_SHIFT                0

/***************************************************************************
 *PHY_STATUS - 40G DDR PHY status register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PHY_STATUS :: reserved0 [31:02] */
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_reserved0_MASK            0xfffffffc
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_reserved0_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_reserved0_BITS            30
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_reserved0_SHIFT           2

/* DDR23_CTL_REGS_0 :: PHY_STATUS :: phy_ready [01:01] */
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_phy_ready_MASK            0x00000002
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_phy_ready_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_phy_ready_BITS            1
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_phy_ready_SHIFT           1

/* DDR23_CTL_REGS_0 :: PHY_STATUS :: phy_pwrup_rsb [00:00] */
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_phy_pwrup_rsb_MASK        0x00000001
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_phy_pwrup_rsb_ALIGN       0
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_phy_pwrup_rsb_BITS        1
#define BCHP_DDR23_CTL_REGS_0_PHY_STATUS_phy_pwrup_rsb_SHIFT       0

/***************************************************************************
 *PARAMS1 - DDR23 Controller Configuration Set #1
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PARAMS1 :: trtp [31:28] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_MASK                    0xf0000000
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_ALIGN                   0
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_BITS                    4
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_SHIFT                   28

/* DDR23_CTL_REGS_0 :: PARAMS1 :: twl [27:24] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_MASK                     0x0f000000
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_ALIGN                    0
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_BITS                     4
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_SHIFT                    24

/* DDR23_CTL_REGS_0 :: PARAMS1 :: tcas [23:20] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_MASK                    0x00f00000
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_ALIGN                   0
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_BITS                    4
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_SHIFT                   20

/* DDR23_CTL_REGS_0 :: PARAMS1 :: twtr [19:16] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_MASK                    0x000f0000
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_ALIGN                   0
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_BITS                    4
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_SHIFT                   16

/* DDR23_CTL_REGS_0 :: PARAMS1 :: reserved0 [15:12] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_reserved0_MASK               0x0000f000
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_reserved0_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_reserved0_BITS               4
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_reserved0_SHIFT              12

/* DDR23_CTL_REGS_0 :: PARAMS1 :: trrd [11:08] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_MASK                    0x00000f00
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_ALIGN                   0
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_BITS                    4
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_SHIFT                   8

/* DDR23_CTL_REGS_0 :: PARAMS1 :: trp [07:04] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_MASK                     0x000000f0
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_ALIGN                    0
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_BITS                     4
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_SHIFT                    4

/* DDR23_CTL_REGS_0 :: PARAMS1 :: trcd [03:00] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_MASK                    0x0000000f
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_ALIGN                   0
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_BITS                    4
#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_SHIFT                   0

/***************************************************************************
 *PARAMS2 - DDR23 Controller Configuration Set #2
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PARAMS2 :: auto_idle [31:31] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_MASK               0x80000000
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_BITS               1
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_SHIFT              31

/* DDR23_CTL_REGS_0 :: PARAMS2 :: clke [30:30] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK                    0x40000000
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_ALIGN                   0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_BITS                    1
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_SHIFT                   30

/* DDR23_CTL_REGS_0 :: PARAMS2 :: use_chr_hgt [29:29] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_MASK             0x20000000
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_ALIGN            0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_BITS             1
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_SHIFT            29

/* DDR23_CTL_REGS_0 :: PARAMS2 :: row_bits [28:27] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_MASK                0x18000000
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_ALIGN               0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_BITS                2
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_SHIFT               27

/* DDR23_CTL_REGS_0 :: PARAMS2 :: sd_col_bits [26:25] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_MASK             0x06000000
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_ALIGN            0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_BITS             2
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_SHIFT            25

/* DDR23_CTL_REGS_0 :: PARAMS2 :: il_sel [24:24] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_MASK                  0x01000000
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_ALIGN                 0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_BITS                  1
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_SHIFT                 24

/* DDR23_CTL_REGS_0 :: PARAMS2 :: dis_itlv [23:23] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_MASK                0x00800000
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_ALIGN               0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_BITS                1
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_SHIFT               23

/* DDR23_CTL_REGS_0 :: PARAMS2 :: cs0_only [22:22] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_MASK                0x00400000
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_ALIGN               0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_BITS                1
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_SHIFT               22

/* DDR23_CTL_REGS_0 :: PARAMS2 :: allow_pictmem_rd [21:21] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_MASK        0x00200000
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_ALIGN       0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_BITS        1
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_SHIFT       21

/* DDR23_CTL_REGS_0 :: PARAMS2 :: bank_bits [20:20] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_MASK               0x00100000
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_BITS               1
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_SHIFT              20

/* DDR23_CTL_REGS_0 :: PARAMS2 :: trfc [19:12] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_MASK                    0x000ff000
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_ALIGN                   0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_BITS                    8
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_SHIFT                   12

/* DDR23_CTL_REGS_0 :: PARAMS2 :: tfaw [11:06] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_MASK                    0x00000fc0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_ALIGN                   0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_BITS                    6
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_SHIFT                   6

/* DDR23_CTL_REGS_0 :: PARAMS2 :: tras [05:00] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_MASK                    0x0000003f
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_ALIGN                   0
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_BITS                    6
#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_SHIFT                   0

/***************************************************************************
 *PARAMS3 - DDR23 Controller Configuration Set #3
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PARAMS3 :: ddr3_reset [31:31] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_MASK              0x80000000
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_BITS              1
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_SHIFT             31

/* DDR23_CTL_REGS_0 :: PARAMS3 :: reserved0 [30:14] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_MASK               0x7fffc000
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_BITS               17
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_SHIFT              14

/* DDR23_CTL_REGS_0 :: PARAMS3 :: twr [13:08] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_twr_MASK                     0x00003f00
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_twr_ALIGN                    0
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_twr_BITS                     6
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_twr_SHIFT                    8

/* DDR23_CTL_REGS_0 :: PARAMS3 :: reserved1 [07:06] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved1_MASK               0x000000c0
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved1_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved1_BITS               2
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved1_SHIFT              6

/* DDR23_CTL_REGS_0 :: PARAMS3 :: ddr_bl [05:05] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_MASK                  0x00000020
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_ALIGN                 0
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_BITS                  1
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_SHIFT                 5

/* DDR23_CTL_REGS_0 :: PARAMS3 :: cmd_2t [04:04] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_MASK                  0x00000010
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_ALIGN                 0
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_BITS                  1
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_SHIFT                 4

/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_mode [03:03] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_MASK             0x00000008
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_ALIGN            0
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_BITS             1
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_SHIFT            3

/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_te_adj [02:02] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_MASK           0x00000004
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_ALIGN          0
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_BITS           1
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_SHIFT          2

/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_le_adj [01:01] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_MASK           0x00000002
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_ALIGN          0
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_BITS           1
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_SHIFT          1

/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_en [00:00] */
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_MASK               0x00000001
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_BITS               1
#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_SHIFT              0

/***************************************************************************
 *REFRESH - DDR23 Controller Automated Refresh Configuration
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: REFRESH :: reserved0 [31:13] */
#define BCHP_DDR23_CTL_REGS_0_REFRESH_reserved0_MASK               0xffffe000
#define BCHP_DDR23_CTL_REGS_0_REFRESH_reserved0_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_REFRESH_reserved0_BITS               19
#define BCHP_DDR23_CTL_REGS_0_REFRESH_reserved0_SHIFT              13

/* DDR23_CTL_REGS_0 :: REFRESH :: enable [12:12] */
#define BCHP_DDR23_CTL_REGS_0_REFRESH_enable_MASK                  0x00001000
#define BCHP_DDR23_CTL_REGS_0_REFRESH_enable_ALIGN                 0
#define BCHP_DDR23_CTL_REGS_0_REFRESH_enable_BITS                  1
#define BCHP_DDR23_CTL_REGS_0_REFRESH_enable_SHIFT                 12

/* DDR23_CTL_REGS_0 :: REFRESH :: period [11:00] */
#define BCHP_DDR23_CTL_REGS_0_REFRESH_period_MASK                  0x00000fff
#define BCHP_DDR23_CTL_REGS_0_REFRESH_period_ALIGN                 0
#define BCHP_DDR23_CTL_REGS_0_REFRESH_period_BITS                  12
#define BCHP_DDR23_CTL_REGS_0_REFRESH_period_SHIFT                 0

/***************************************************************************
 *REFRESH_CMD - Host Initiated Refresh Control
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: REFRESH_CMD :: reserved0 [31:16] */
#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_reserved0_MASK           0xffff0000
#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_reserved0_ALIGN          0
#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_reserved0_BITS           16
#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_reserved0_SHIFT          16

/* DDR23_CTL_REGS_0 :: REFRESH_CMD :: cmd [15:00] */
#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_cmd_MASK                 0x0000ffff
#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_cmd_ALIGN                0
#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_cmd_BITS                 16
#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_cmd_SHIFT                0

/***************************************************************************
 *PRECHARGE_CMD - Host Initiated Precharge Control
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PRECHARGE_CMD :: reserved0 [31:16] */
#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_reserved0_MASK         0xffff0000
#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_reserved0_ALIGN        0
#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_reserved0_BITS         16
#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_reserved0_SHIFT        16

/* DDR23_CTL_REGS_0 :: PRECHARGE_CMD :: cmd [15:00] */
#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_cmd_MASK               0x0000ffff
#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_cmd_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_cmd_BITS               16
#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_cmd_SHIFT              0

/***************************************************************************
 *LOAD_MODE_CMD - Host Initiated Load Mode Control
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: LOAD_MODE_CMD :: reserved0 [31:16] */
#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_reserved0_MASK         0xffff0000
#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_reserved0_ALIGN        0
#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_reserved0_BITS         16
#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_reserved0_SHIFT        16

/* DDR23_CTL_REGS_0 :: LOAD_MODE_CMD :: cmd [15:00] */
#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_cmd_MASK               0x0000ffff
#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_cmd_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_cmd_BITS               16
#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_cmd_SHIFT              0

/***************************************************************************
 *LOAD_EMODE_CMD - Host Initiated Load Extended Mode Control
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: LOAD_EMODE_CMD :: reserved0 [31:16] */
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_reserved0_MASK        0xffff0000
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_reserved0_ALIGN       0
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_reserved0_BITS        16
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_reserved0_SHIFT       16

/* DDR23_CTL_REGS_0 :: LOAD_EMODE_CMD :: cmd [15:00] */
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_cmd_MASK              0x0000ffff
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_cmd_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_cmd_BITS              16
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_cmd_SHIFT             0

/***************************************************************************
 *LOAD_EMODE2_CMD - Host Initiated Load Extended Mode #2 Control
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: LOAD_EMODE2_CMD :: reserved0 [31:16] */
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_reserved0_MASK       0xffff0000
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_reserved0_ALIGN      0
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_reserved0_BITS       16
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_reserved0_SHIFT      16

/* DDR23_CTL_REGS_0 :: LOAD_EMODE2_CMD :: cmd [15:00] */
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_cmd_MASK             0x0000ffff
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_cmd_ALIGN            0
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_cmd_BITS             16
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_cmd_SHIFT            0

/***************************************************************************
 *LOAD_EMODE3_CMD - Host Initiated Load Extended Mode #3 Control
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: LOAD_EMODE3_CMD :: reserved0 [31:16] */
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_reserved0_MASK       0xffff0000
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_reserved0_ALIGN      0
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_reserved0_BITS       16
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_reserved0_SHIFT      16

/* DDR23_CTL_REGS_0 :: LOAD_EMODE3_CMD :: cmd [15:00] */
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_cmd_MASK             0x0000ffff
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_cmd_ALIGN            0
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_cmd_BITS             16
#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_cmd_SHIFT            0

/***************************************************************************
 *ZQ_CALIBRATE - Host Initiated ZQ Calibration Cycle
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: ZQ_CALIBRATE :: reserved0 [31:16] */
#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_reserved0_MASK          0xffff0000
#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_reserved0_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_reserved0_BITS          16
#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_reserved0_SHIFT         16

/* DDR23_CTL_REGS_0 :: ZQ_CALIBRATE :: cmd [15:00] */
#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_cmd_MASK                0x0000ffff
#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_cmd_ALIGN               0
#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_cmd_BITS                16
#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_cmd_SHIFT               0

/***************************************************************************
 *CMD_STATUS - Host Command Interface Status
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: CMD_STATUS :: reserved0 [31:01] */
#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_reserved0_MASK            0xfffffffe
#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_reserved0_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_reserved0_BITS            31
#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_reserved0_SHIFT           1

/* DDR23_CTL_REGS_0 :: CMD_STATUS :: status [00:00] */
#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_status_MASK               0x00000001
#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_status_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_status_BITS               1
#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_status_SHIFT              0

/***************************************************************************
 *LATENCY - DDR2 Controller Access Latency Control
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: LATENCY :: reserved0 [31:10] */
#define BCHP_DDR23_CTL_REGS_0_LATENCY_reserved0_MASK               0xfffffc00
#define BCHP_DDR23_CTL_REGS_0_LATENCY_reserved0_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_LATENCY_reserved0_BITS               22
#define BCHP_DDR23_CTL_REGS_0_LATENCY_reserved0_SHIFT              10

/* DDR23_CTL_REGS_0 :: LATENCY :: limit [09:00] */
#define BCHP_DDR23_CTL_REGS_0_LATENCY_limit_MASK                   0x000003ff
#define BCHP_DDR23_CTL_REGS_0_LATENCY_limit_ALIGN                  0
#define BCHP_DDR23_CTL_REGS_0_LATENCY_limit_BITS                   10
#define BCHP_DDR23_CTL_REGS_0_LATENCY_limit_SHIFT                  0

/***************************************************************************
 *SEMAPHORE0 - Semaphore Register #0
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: SEMAPHORE0 :: reserved0 [31:01] */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_reserved0_MASK            0xfffffffe
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_reserved0_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_reserved0_BITS            31
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_reserved0_SHIFT           1

/* DDR23_CTL_REGS_0 :: SEMAPHORE0 :: enable [00:00] */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_enable_MASK               0x00000001
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_enable_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_enable_BITS               1
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_enable_SHIFT              0

/***************************************************************************
 *SEMAPHORE1 - Semaphore Register #1
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: SEMAPHORE1 :: reserved0 [31:01] */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_reserved0_MASK            0xfffffffe
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_reserved0_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_reserved0_BITS            31
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_reserved0_SHIFT           1

/* DDR23_CTL_REGS_0 :: SEMAPHORE1 :: enable [00:00] */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_enable_MASK               0x00000001
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_enable_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_enable_BITS               1
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_enable_SHIFT              0

/***************************************************************************
 *SEMAPHORE2 - Semaphore Register #2
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: SEMAPHORE2 :: reserved0 [31:01] */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_reserved0_MASK            0xfffffffe
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_reserved0_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_reserved0_BITS            31
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_reserved0_SHIFT           1

/* DDR23_CTL_REGS_0 :: SEMAPHORE2 :: enable [00:00] */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_enable_MASK               0x00000001
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_enable_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_enable_BITS               1
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_enable_SHIFT              0

/***************************************************************************
 *SEMAPHORE3 - Semaphore Register #3
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: SEMAPHORE3 :: reserved0 [31:01] */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_reserved0_MASK            0xfffffffe
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_reserved0_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_reserved0_BITS            31
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_reserved0_SHIFT           1

/* DDR23_CTL_REGS_0 :: SEMAPHORE3 :: enable [00:00] */
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_enable_MASK               0x00000001
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_enable_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_enable_BITS               1
#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_enable_SHIFT              0

/***************************************************************************
 *SCRATCH - Scratch Register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: SCRATCH :: scratch [31:00] */
#define BCHP_DDR23_CTL_REGS_0_SCRATCH_scratch_MASK                 0xffffffff
#define BCHP_DDR23_CTL_REGS_0_SCRATCH_scratch_ALIGN                0
#define BCHP_DDR23_CTL_REGS_0_SCRATCH_scratch_BITS                 32
#define BCHP_DDR23_CTL_REGS_0_SCRATCH_scratch_SHIFT                0

/***************************************************************************
 *STRIPE_WIDTH - Stripe Width
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: STRIPE_WIDTH :: reserved0 [31:02] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_reserved0_MASK          0xfffffffc
#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_reserved0_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_reserved0_BITS          30
#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_reserved0_SHIFT         2

/* DDR23_CTL_REGS_0 :: STRIPE_WIDTH :: swidth [01:00] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_swidth_MASK             0x00000003
#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_swidth_ALIGN            0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_swidth_BITS             2
#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_swidth_SHIFT            0

/***************************************************************************
 *STRIPE_HEIGHT_0 - Stripe Height for picture buffers 0 through 23
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: reserved0 [31:27] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved0_MASK       0xf8000000
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved0_ALIGN      0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved0_BITS       5
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved0_SHIFT      27

/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: chroma_height [26:16] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_chroma_height_MASK   0x07ff0000
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_chroma_height_ALIGN  0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_chroma_height_BITS   11
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_chroma_height_SHIFT  16

/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: reserved1 [15:11] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved1_MASK       0x0000f800
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved1_ALIGN      0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved1_BITS       5
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved1_SHIFT      11

/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: luma_height [10:00] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_luma_height_MASK     0x000007ff
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_luma_height_ALIGN    0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_luma_height_BITS     11
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_luma_height_SHIFT    0

/***************************************************************************
 *STRIPE_HEIGHT_1 - Stripe Height for picture buffers 24 through 27
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: reserved0 [31:27] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved0_MASK       0xf8000000
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved0_ALIGN      0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved0_BITS       5
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved0_SHIFT      27

/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: chroma_height [26:16] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_chroma_height_MASK   0x07ff0000
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_chroma_height_ALIGN  0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_chroma_height_BITS   11
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_chroma_height_SHIFT  16

/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: reserved1 [15:11] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved1_MASK       0x0000f800
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved1_ALIGN      0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved1_BITS       5
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved1_SHIFT      11

/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: luma_height [10:00] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_luma_height_MASK     0x000007ff
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_luma_height_ALIGN    0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_luma_height_BITS     11
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_luma_height_SHIFT    0

/***************************************************************************
 *STRIPE_HEIGHT_2 - Stripe Height for picture buffers 28 through 31
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: reserved0 [31:27] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved0_MASK       0xf8000000
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved0_ALIGN      0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved0_BITS       5
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved0_SHIFT      27

/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: chroma_height [26:16] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_chroma_height_MASK   0x07ff0000
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_chroma_height_ALIGN  0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_chroma_height_BITS   11
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_chroma_height_SHIFT  16

/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: reserved1 [15:11] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved1_MASK       0x0000f800
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved1_ALIGN      0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved1_BITS       5
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved1_SHIFT      11

/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: luma_height [10:00] */
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_luma_height_MASK     0x000007ff
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_luma_height_ALIGN    0
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_luma_height_BITS     11
#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_luma_height_SHIFT    0

/***************************************************************************
 *PLL_CONFIG - PLL Configuration Register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PLL_CONFIG :: reserved0 [31:02] */
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_reserved0_MASK            0xfffffffc
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_reserved0_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_reserved0_BITS            30
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_reserved0_SHIFT           2

/* DDR23_CTL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_RESET_MASK                0x00000002
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_RESET_ALIGN               0
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_RESET_BITS                1
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_RESET_SHIFT               1

/* DDR23_CTL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_PWRDN_MASK                0x00000001
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_PWRDN_ALIGN               0
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_PWRDN_BITS                1
#define BCHP_DDR23_CTL_REGS_0_PLL_CONFIG_PWRDN_SHIFT               0

/***************************************************************************
 *PLL_STATUS - PLL Status Register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PLL_STATUS :: reserved0 [31:16] */
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_reserved0_MASK            0xffff0000
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_reserved0_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_reserved0_BITS            16
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_reserved0_SHIFT           16

/* DDR23_CTL_REGS_0 :: PLL_STATUS :: STATUS [15:04] */
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_STATUS_MASK               0x0000fff0
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_STATUS_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_STATUS_BITS               12
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_STATUS_SHIFT              4

/* DDR23_CTL_REGS_0 :: PLL_STATUS :: reserved1 [03:02] */
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_reserved1_MASK            0x0000000c
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_reserved1_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_reserved1_BITS            2
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_reserved1_SHIFT           2

/* DDR23_CTL_REGS_0 :: PLL_STATUS :: LOCK_LOST [01:01] */
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_LOCK_LOST_MASK            0x00000002
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_LOCK_LOST_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_LOCK_LOST_BITS            1
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT           1

/* DDR23_CTL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_LOCK_MASK                 0x00000001
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_LOCK_ALIGN                0
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_LOCK_BITS                 1
#define BCHP_DDR23_CTL_REGS_0_PLL_STATUS_LOCK_SHIFT                0

/***************************************************************************
 *PLL_CONTROL - PLL Control Register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PLL_CONTROL :: reserved0 [31:30] */
#define BCHP_DDR23_CTL_REGS_0_PLL_CONTROL_reserved0_MASK           0xc0000000
#define BCHP_DDR23_CTL_REGS_0_PLL_CONTROL_reserved0_ALIGN          0
#define BCHP_DDR23_CTL_REGS_0_PLL_CONTROL_reserved0_BITS           2
#define BCHP_DDR23_CTL_REGS_0_PLL_CONTROL_reserved0_SHIFT          30

/* DDR23_CTL_REGS_0 :: PLL_CONTROL :: i_pll_ctrl [29:00] */
#define BCHP_DDR23_CTL_REGS_0_PLL_CONTROL_i_pll_ctrl_MASK          0x3fffffff
#define BCHP_DDR23_CTL_REGS_0_PLL_CONTROL_i_pll_ctrl_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_PLL_CONTROL_i_pll_ctrl_BITS          30
#define BCHP_DDR23_CTL_REGS_0_PLL_CONTROL_i_pll_ctrl_SHIFT         0

/***************************************************************************
 *PLL_GAIN_CONTROL - PLL Gain Control Register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PLL_GAIN_CONTROL :: reserved0 [31:10] */
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_reserved0_MASK      0xfffffc00
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_reserved0_ALIGN     0
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_reserved0_BITS      22
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_reserved0_SHIFT     10

/* DDR23_CTL_REGS_0 :: PLL_GAIN_CONTROL :: i_kp [09:06] */
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_kp_MASK           0x000003c0
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_kp_ALIGN          0
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_kp_BITS           4
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_kp_SHIFT          6

/* DDR23_CTL_REGS_0 :: PLL_GAIN_CONTROL :: i_ki [05:03] */
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_ki_MASK           0x00000038
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_ki_ALIGN          0
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_ki_BITS           3
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_ki_SHIFT          3

/* DDR23_CTL_REGS_0 :: PLL_GAIN_CONTROL :: i_ka [02:00] */
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_ka_MASK           0x00000007
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_ka_ALIGN          0
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_ka_BITS           3
#define BCHP_DDR23_CTL_REGS_0_PLL_GAIN_CONTROL_i_ka_SHIFT          0

/***************************************************************************
 *PLL_DIVIDERS - PLL Dividers Register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:24] */
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved0_MASK          0xff000000
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved0_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved0_BITS          8
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT         24

/* DDR23_CTL_REGS_0 :: PLL_DIVIDERS :: M1DIV [23:16] */
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_M1DIV_MASK              0x00ff0000
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_M1DIV_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_M1DIV_BITS              8
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_M1DIV_SHIFT             16

/* DDR23_CTL_REGS_0 :: PLL_DIVIDERS :: reserved1 [15:15] */
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved1_MASK          0x00008000
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved1_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved1_BITS          1
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved1_SHIFT         15

/* DDR23_CTL_REGS_0 :: PLL_DIVIDERS :: PDIV [14:12] */
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_PDIV_MASK               0x00007000
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_PDIV_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_PDIV_BITS               3
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT              12

/* DDR23_CTL_REGS_0 :: PLL_DIVIDERS :: reserved2 [11:10] */
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved2_MASK          0x00000c00
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved2_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved2_BITS          2
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_reserved2_SHIFT         10

/* DDR23_CTL_REGS_0 :: PLL_DIVIDERS :: NDIV [09:00] */
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_NDIV_MASK               0x000003ff
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_NDIV_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_NDIV_BITS               10
#define BCHP_DDR23_CTL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT              0

/***************************************************************************
 *PLL_SS_CONTROL - PLL Spread Spectrum Control Register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PLL_SS_CONTROL :: reserved0 [31:26] */
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_reserved0_MASK        0xfc000000
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_reserved0_ALIGN       0
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_reserved0_BITS        6
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_reserved0_SHIFT       26

/* DDR23_CTL_REGS_0 :: PLL_SS_CONTROL :: SPARE [25:08] */
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_SPARE_MASK            0x03ffff00
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_SPARE_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_SPARE_BITS            18
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_SPARE_SHIFT           8

/* DDR23_CTL_REGS_0 :: PLL_SS_CONTROL :: reserved1 [07:01] */
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_reserved1_MASK        0x000000fe
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_reserved1_ALIGN       0
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_reserved1_BITS        7
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_reserved1_SHIFT       1

/* DDR23_CTL_REGS_0 :: PLL_SS_CONTROL :: MODE [00:00] */
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_MODE_MASK             0x00000001
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_MODE_ALIGN            0
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_MODE_BITS             1
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_CONTROL_MODE_SHIFT            0

/***************************************************************************
 *PLL_SS_LIMIT - PLL Spread Spectrum Limit Register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PLL_SS_LIMIT :: reserved0 [31:22] */
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_LIMIT_reserved0_MASK          0xffc00000
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_LIMIT_reserved0_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_LIMIT_reserved0_BITS          10
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_LIMIT_reserved0_SHIFT         22

/* DDR23_CTL_REGS_0 :: PLL_SS_LIMIT :: LIMIT [21:00] */
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_LIMIT_LIMIT_MASK              0x003fffff
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_LIMIT_LIMIT_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_LIMIT_LIMIT_BITS              22
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_LIMIT_LIMIT_SHIFT             0

/***************************************************************************
 *PLL_SS_STEP - PLL Spread Spectrum Step Register
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PLL_SS_STEP :: reserved0 [31:16] */
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_STEP_reserved0_MASK           0xffff0000
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_STEP_reserved0_ALIGN          0
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_STEP_reserved0_BITS           16
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_STEP_reserved0_SHIFT          16

/* DDR23_CTL_REGS_0 :: PLL_SS_STEP :: STEP [15:00] */
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_STEP_STEP_MASK                0x0000ffff
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_STEP_STEP_ALIGN               0
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_STEP_STEP_BITS                16
#define BCHP_DDR23_CTL_REGS_0_PLL_SS_STEP_STEP_SHIFT               0

/***************************************************************************
 *VDL_CTL - Dynamic VDL Changes Control
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: VDL_CTL :: reserved0 [31:01] */
#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_reserved0_MASK               0xfffffffe
#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_reserved0_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_reserved0_BITS               31
#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_reserved0_SHIFT              1

/* DDR23_CTL_REGS_0 :: VDL_CTL :: enable [00:00] */
#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_enable_MASK                  0x00000001
#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_enable_ALIGN                 0
#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_enable_BITS                  1
#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_enable_SHIFT                 0

/***************************************************************************
 *VDL_ADR_BASE - Dynamic VDL Changes Base Address
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: VDL_ADR_BASE :: addr [31:00] */
#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_BASE_addr_MASK               0xffffffff
#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_BASE_addr_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_BASE_addr_BITS               32
#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_BASE_addr_SHIFT              0

/***************************************************************************
 *VDL_ADR_END - Dynamic VDL Changes End Address
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: VDL_ADR_END :: addr [31:00] */
#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_END_addr_MASK                0xffffffff
#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_END_addr_ALIGN               0
#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_END_addr_BITS                32
#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_END_addr_SHIFT               0

/***************************************************************************
 *PMON_CTL - Performance Monitoring Control
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PMON_CTL :: reserved0 [31:01] */
#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_reserved0_MASK              0xfffffffe
#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_reserved0_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_reserved0_BITS              31
#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_reserved0_SHIFT             1

/* DDR23_CTL_REGS_0 :: PMON_CTL :: enable [00:00] */
#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_enable_MASK                 0x00000001
#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_enable_ALIGN                0
#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_enable_BITS                 1
#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_enable_SHIFT                0

/***************************************************************************
 *PMON_PERIOD - Performance Monitoring Period Control
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PMON_PERIOD :: reserved0 [31:24] */
#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_reserved0_MASK           0xff000000
#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_reserved0_ALIGN          0
#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_reserved0_BITS           8
#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_reserved0_SHIFT          24

/* DDR23_CTL_REGS_0 :: PMON_PERIOD :: count [23:00] */
#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_count_MASK               0x00ffffff
#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_count_ALIGN              0
#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_count_BITS               24
#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_count_SHIFT              0

/***************************************************************************
 *PMON_CYCLE_CNT - Performance Monitoring Active Cycles Count
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PMON_CYCLE_CNT :: reserved0 [31:24] */
#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_reserved0_MASK        0xff000000
#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_reserved0_ALIGN       0
#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_reserved0_BITS        8
#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_reserved0_SHIFT       24

/* DDR23_CTL_REGS_0 :: PMON_CYCLE_CNT :: count [23:00] */
#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_count_MASK            0x00ffffff
#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_count_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_count_BITS            24
#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_count_SHIFT           0

/***************************************************************************
 *PMON_IDLE_CNT - Performance Monitoring Idle Cycles Count
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PMON_IDLE_CNT :: reserved0 [31:24] */
#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_reserved0_MASK         0xff000000
#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_reserved0_ALIGN        0
#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_reserved0_BITS         8
#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_reserved0_SHIFT        24

/* DDR23_CTL_REGS_0 :: PMON_IDLE_CNT :: count [23:00] */
#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_count_MASK             0x00ffffff
#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_count_ALIGN            0
#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_count_BITS             24
#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_count_SHIFT            0

/***************************************************************************
 *PMON_RD_CNT1 - Performance Monitoring Data Channel #1 Read Accesses Count
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PMON_RD_CNT1 :: reserved0 [31:24] */
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_reserved0_MASK          0xff000000
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_reserved0_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_reserved0_BITS          8
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_reserved0_SHIFT         24

/* DDR23_CTL_REGS_0 :: PMON_RD_CNT1 :: count [23:00] */
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_count_MASK              0x00ffffff
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_count_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_count_BITS              24
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_count_SHIFT             0

/***************************************************************************
 *PMON_RD_CNT2 - Performance Monitoring Data Channel #2 Read Accesses Count
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PMON_RD_CNT2 :: reserved0 [31:24] */
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_reserved0_MASK          0xff000000
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_reserved0_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_reserved0_BITS          8
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_reserved0_SHIFT         24

/* DDR23_CTL_REGS_0 :: PMON_RD_CNT2 :: count [23:00] */
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_count_MASK              0x00ffffff
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_count_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_count_BITS              24
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_count_SHIFT             0

/***************************************************************************
 *PMON_RD_CNT3 - Performance Monitoring Data Channel #3 Read Accesses Count
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PMON_RD_CNT3 :: reserved0 [31:24] */
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_reserved0_MASK          0xff000000
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_reserved0_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_reserved0_BITS          8
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_reserved0_SHIFT         24

/* DDR23_CTL_REGS_0 :: PMON_RD_CNT3 :: count [23:00] */
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_count_MASK              0x00ffffff
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_count_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_count_BITS              24
#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_count_SHIFT             0

/***************************************************************************
 *PMON_WR_CNT1 - Performance Monitoring Data Channel #1 Write Accesses Count
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PMON_WR_CNT1 :: reserved0 [31:24] */
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_reserved0_MASK          0xff000000
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_reserved0_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_reserved0_BITS          8
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_reserved0_SHIFT         24

/* DDR23_CTL_REGS_0 :: PMON_WR_CNT1 :: count [23:00] */
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_count_MASK              0x00ffffff
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_count_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_count_BITS              24
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_count_SHIFT             0

/***************************************************************************
 *PMON_WR_CNT2 - Performance Monitoring Data Channel #2 Write Accesses Count
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PMON_WR_CNT2 :: reserved0 [31:24] */
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_reserved0_MASK          0xff000000
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_reserved0_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_reserved0_BITS          8
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_reserved0_SHIFT         24

/* DDR23_CTL_REGS_0 :: PMON_WR_CNT2 :: count [23:00] */
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_count_MASK              0x00ffffff
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_count_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_count_BITS              24
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_count_SHIFT             0

/***************************************************************************
 *PMON_WR_CNT3 - Performance Monitoring Data Channel #3 Write Accesses Count
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PMON_WR_CNT3 :: reserved0 [31:24] */
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_reserved0_MASK          0xff000000
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_reserved0_ALIGN         0
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_reserved0_BITS          8
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_reserved0_SHIFT         24

/* DDR23_CTL_REGS_0 :: PMON_WR_CNT3 :: count [23:00] */
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_count_MASK              0x00ffffff
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_count_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_count_BITS              24
#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_count_SHIFT             0

/***************************************************************************
 *UPDATE_VDL - RAM Macro TM Control
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: UPDATE_VDL :: reserved0 [31:02] */
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_reserved0_MASK            0xfffffffc
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_reserved0_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_reserved0_BITS            30
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_reserved0_SHIFT           2

/* DDR23_CTL_REGS_0 :: UPDATE_VDL :: force [01:01] */
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_force_MASK                0x00000002
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_force_ALIGN               0
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_force_BITS                1
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_force_SHIFT               1

/* DDR23_CTL_REGS_0 :: UPDATE_VDL :: refresh [00:00] */
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_MASK              0x00000001
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_BITS              1
#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_SHIFT             0

/***************************************************************************
 *PICT_BASE%i - Picture Buffer Base Address Ram
 ***************************************************************************/
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_BASE                0x00000100
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_START               0
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_END                 63
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_ELEMENT_SIZE        32

/***************************************************************************
 *PICT_BASE%i - Picture Buffer Base Address Ram
 ***************************************************************************/
/* DDR23_CTL_REGS_0 :: PICT_BASEi :: address [31:12] */
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_address_MASK              0xfffff000
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_address_ALIGN             0
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_address_BITS              20
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_address_SHIFT             12

/* DDR23_CTL_REGS_0 :: PICT_BASEi :: reserved0 [11:00] */
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_reserved0_MASK            0x00000fff
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_reserved0_ALIGN           0
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_reserved0_BITS            12
#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_reserved0_SHIFT           0


#endif /* #ifndef BCHP_DDR23_CTL_REGS_0_H__ */

/* End of File */
